Low density parity check (LDPC) codes are prevalently used in data storage technologies and data transmission technologies for providing data integrity. Message passing decoders are commonly used for decoding LDPC codes. These decoders provide good error correction capability at the cost of complex silicon on chip (SoC) implementation.
Existing systems use various bit flipping (BF) decoders that flip the bits based on information available for variable nodes. BF decoders are easy to implement on hardware and provide significant area and power savings.
Generally, a BF decoder uses a set of rules to decide whether a bit should be flipped or not. The rules are generated heuristically. The correction capability, such as the bit error rate (BER) performance of the BF decoder depends on the used rules. In many situations, it is challenging to find, at least heuristically, the set of rules that achieves a particular BER performance. For example, irregular LDPC codes have degrees (e.g., number of connected check nodes) that vary across the variable nodes. The variability in the degrees exacerbate the challenge of generating the proper rules to achieves the particular BER performance.